Abstract Data Plane Compiler (Mar/2016 – Nov/2019). Funded by Ericsson.
SDN approaches (e.g. OpenFlow 1.x) expose new control knobs for programming the network but the knobs’ functions are largely dictated by the fixed functionality of the forwarding devices. The feature mismatch on programmable dataplanes causes an “information leakage” from the SDN switches to the controller(s), requiring target/platform-specific details to be considered by developers of the SDN control application/controller. The actual performance, feature support, and overall program portability depend on the internal, hardwired characteristics of the data plane targets, contributing to costly development-release cycles and feature mismatch/inconsistencies, as evidenced by the amount of optional features in OpenFlow, an actual hazard that became clear during OpenFlow 1.3 testing and interop activities. If the functionally of forwarding devices needs to be (dynamically) reprogrammed to define new protocol stacks and associated packet parsing and table processing functions (i.e. dataplane pipeline), a programmable interface (not just configurable) needs to be developed (e.g., P4) for which corresponding backends (aka run-time compilers) are required on a switch / dataplane target basis. Striking the right balance between fixed support for protocols to a general-purpose programming language is one of the missing pieces of SDN. Quoting [OVS-P4]: “Numerous questions remain about the relationship between P4, OpenFlow, and OVS”. The key research questions of this project revolve around understanding the evolving software stack of SDN programmable data planes with regard to the actual portability and performance levels of the different solutions (i.e. combinations of data plane targets, intermediate languages, compilers, and higher-level abstractions).
- Pattam Gyanesh Patra, Fabricio Rodriguez, Juan Sebastian Mejia, Daniel Lazkani Feferman, Levente Csikor, Christian Esteve Rothenberg, Gergely Pongrácz. “Towards a Sweet Spot of Dataplane Programmability, Portability and Performance: On the Scalability of Multi-Architecture P4 Pipelines”. In IEEE JSAC issue on Scalability Issues and Solutions for Software Defined Networks, Sep. 2018. 10.1109/JSAC.2018.2871288 [preprint]
- F. Rodriguez, P. G. Patra, L. Csikor, C. Rothenberg, P. Vörös, S. Laki, and G. Pongrácz, “BB-Gen: a packet crafter for P4 target evaluation”. In ACM SIGCOMM’18 demo and poster session, 2018 [PDF]
- Pattam Gyanesh Patra, Christian Esteve Rothenberg, Gergely Pongrácz. “MACSAD: High Performance Dataplane Applications on the Move”. In IEEE 18th International Conference on High Performance Switching and Routing (HPSR), Campinas, Brazil, Jun. 2017. [PDF]
- Gyanesh Kumar Patra, Christian Esteve Rothenberg, Gergely Pongrácz. “MACSAD: Multi-Architecture Compiler System for Abstract Dataplanes (aka Partnering P4 with ODP)”. In ACM SIGCOMM 2016 Poster & Demo Session, Aug 2016. [PDF]